Functional Verification of High Performance Adders in COQ
نویسندگان
چکیده
منابع مشابه
Functional Verification of High Performance Adders in COQ
Let us know how access to this document benefits you. Addition arithmetic design plays a crucial role in high performance digital systems. The paper proposes a systematic method to formalize and verify adders in a formal proof assistant Coq. The proposed approach succeeds in formalizing the gate-level implementations and verifying the functional correctness of the most important adders of inter...
متن کاملVerification of Floating-Point Adders
The floating-point division bug in Intel's Pentium processor and the overflow flag erratum of the FIST instruction in Intel's Pentium Pro and Pentium II processor have demonstrated the importance and the difficulty of verifying floating-point arithmetic circuits. In this paper, we present a "black box" version of verification of FP adders. In our approach, FP adders are verified by an extended ...
متن کاملHigh Performance CNFET-based Ternary Full Adders
This paper investigates the use of carbon nanotube field effect transistors (CNFETs) for the design of ternary full adder cells. The proposed circuits have been designed based on the unique properties of CNFETs such as having desired threshold voltages by adjusting diameter of the CNFETs gate nanotubes. The proposed circuits are examined using HSPICE simulator with the standard 32 nm CNFET tech...
متن کاملHybrid System verification in Coq
This internship is intended to improve the abstraction method described by Alur in [2], and implemented in Coq in Nimegen [5,7] for proving the safety of hybrid systems.
متن کاملReducing power of functional units in high-performance processors by checking instruction codes and resizing adders
A hardware technique to reduce static and dynamic power consumption in functional units of 64-bit high-performance processors is presented here. The instructions that require an adder have been studied it can be concluded and that, there is a large percentage of instruction where one of the two source operands is always narrow and does not require a 64-bit adder. Furthermore, by analysing the e...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Journal of Applied Mathematics
سال: 2014
ISSN: 1110-757X,1687-0042
DOI: 10.1155/2014/197252